How do I setup word sychronisation with Altera Soft LVDS with external PLL on MAX10

Hi,

I successfully setup a SerDes link between two MAX10 devices with the soft LVDS IP and internal (!)

PLL. The devices are connected by two LVDS signals - one for clock and one for data.

SerDes factor is 1:10. Clock is 10MHz, bitrate is 100Mbit/s.

Now I need to modify the design to use the SerDes IP with an _external_ PLL. I modified the IP with the mega wizard

and switched on "use external PLL". The component now looks like this:

component lvds_rx_extpll is

port (

rx_inclock : in std_logic := 'X'; -- rx_inclock

rx_in : in std_logic := 'X'; -- rx_in

rx_out : out std_logic_vector(9 downto 0) -- rx_out

);

end component lvds_rx_extpll;

In general the design works fine. But how is the word synchronisation done in this case? With internal PLL the rx_out data

is sychronized to the edge of the 10MHz signal. But with external PLL the IP has no chance to do so, because it only gets the 100MHz clock

from the PLL (rx_inclock).

How do I implement the SerDes receiver with external PLL that behaves identical to the receiver with internal PLL? Do I have to use the bitslip function by hand?

Or how can I bring the 10MHz clock into the game?

So here is my (ext.) PLL:

component serdes_pll

PORT (

areset : IN STD_LOGIC := '0';

inclk0 : IN STD_LOGIC := '0'; -- 10MHz coming from transmitter

c0 : OUT STD_LOGIC ; -- 100MHz -> rx_inclock

c1 : OUT STD_LOGIC ; -- 10MHz

locked : OUT STD_LOGIC

);

end component;

This is my previous working receiver with internal PLL with rx_out vector beeing valid on rx_outclock:

-- serdes receiver with internal PLL

component lvds_rx is

port (

pll_areset : in std_logic;

rx_inclock : in std_logic; -- 10MHz from transmitter

rx_in : in std_logic; -- data from transmitter

rx_out : out std_logic_vector(9 downto 0); -- deserialized word

rx_outclock : out std_logic; -- 10Mhz clock for rx_out

rx_locked : out std_logic

);

end component;

Matthias