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Honored Contributor
Honored ContributorHow do I setup word sychronisation with Altera Soft LVDS with external PLL on MAX10
Hi, I successfully setup a SerDes link between two MAX10 devices with the soft LVDS IP and internal (!) PLL. The devices are connected by two LVDS signals - one for clock and one for data. ...
Altera_ForumHonored Contributor
Honored ContributorSearch around for "altlvds align" and you'll find several threads here and elsewhere talking about the issue of aligning data coming out of the ALTLVDS_RX.
Long story short, you feed the RX path a known pattern and jog the 'align' bit to shift the word until it matches the pattern you expect. In your case, you probably want to supply ALTLVDS_RX with your 10MHz clock as an additional 'rx_in' to key off as a framing signal.
