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Altera_Forum
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18 years ago

How Could I use DDR in CyClone III Starter kit successfully?

Hello,

I try to use the DDR in Cyclone III starter kit ,But I try it a lot of times ,It is not success ,even I do not know why I cannot to use the DDR IP.When I generate the project it hints error. Could you give me a detail steps ,thanks ,I use Quartus II 7.1.

Expecting your help !

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Please check you have valid license to use DDR IP Megacore. If you have valid license then you should be able to generate your required system through SOPC Builder, you can use DDR SDRAM High Performance Controller with PSC A2S56D40CTP-G5 as Memory Preset for Cyclone III Starter Kit

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    --- Quote Start ---

    Please check you have valid license to use DDR IP Megacore. If you have valid license then you should be able to generate your required system through SOPC Builder, you can use DDR SDRAM High Performance Controller with PSC A2S56D40CTP-G5 as Memory Preset for Cyclone III Starter Kit

    --- Quote End ---

    I have tried the method ,but I do not know how to assign the Pins including the generated PLL to Sopc,could you tell me what is DQS Groups ,what is it's meaning and how to use it,thanks!If possible ,could you give me any document about how to compile DDR successfully.Expecting your answers thanks very much!
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    I admit, that setup of DDR II pins and required I/O standard is a somewhat complex action. When designing a DDR interface on a new board from the scratch, the Megawizard guides you through an interactive process, where suitable pins are choosen and Tcl files with I/O settings are generated. If you decided to define the DDR mapping without the Megawizard to choose the pins, you should have a good understanding of the DDR pin group requirements.

    However, with CIII starter board, the situation is very easy to my opinion, cause a complete DDR II example design including all necessary pin settings already exists. It's in the cycloneiii_3c25_start_niosii_standard folder. The DDR related assignments can be used also for a non NIOS II related design. altmemddr_pin_assignments.tcl together with the pin mapping defined in cycloneiii_3c25_start_niosii_standard.qsf and the Wizard generated HP DDR controller design top altmemddr.v can be starting point for an own DDR II design, that fits the Dev Kit supplied hardware.
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    I have compiled the DDR ,but in the last steps(EDA netlist Writer) it told me following:Error: Can't generate netlist output files because the file "E:/2008-04-01/DDR_71/auk_ddr_hp_controller.vhd" is an OpenCore Plus time-limited file

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Cause the DDR II controller is encrypted Altera IP, you can't generate a netlist for this design entity. You can generate a simulation netlist from Megawizard, if you wan't to perform e. g. a ModelSim simulation. Where do you need a netlist for?

    For a permanent programming file that includes the DDR II controller, you need a Quartus subscription license.