Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorHow can I translated VHDL to Verilog HDL.
How can I translated VHDL to Verilog HDL. The problem is how can I deal with the posedge and negedge with the same signal.
process(Timer)
begin
if Timer'event and Timer='1' then --Time...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Try this: always @(Timer) begin if (Timer) begin trise = 1; start = 1; end else begin trise = 0; hold = 1; end end Of course, this is not synthesizable but should work in simulation. Regards, Harald --- Quote End --- Thanx, Harald, it seems better than what I think! :)
