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Altera_Forum's avatar
Altera_Forum
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16 years ago

How can I translated VHDL to Verilog HDL.

How can I translated VHDL to Verilog HDL. The problem is how can I deal with the posedge and negedge with the same signal. process(Timer) begin if Timer'event and Timer='1' then --Time...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Try this:

always @(Timer)

begin

if (Timer)

begin

trise = 1;

start = 1;

end

else

begin

trise = 0;

hold = 1;

end

end

Of course, this is not synthesizable but should work in simulation.

Regards,

Harald