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Altera_Forum
Honored Contributor
Honored ContributorHow can I translated VHDL to Verilog HDL.
How can I translated VHDL to Verilog HDL.
The problem is how can I deal with the posedge and negedge with the same signal.
process(Timer)
begin
if Timer'event and Timer='1' then --Timer rising edge.
trise<='1';
start = 1;
elsif Timer'event and Timer='0' then --Timer falling edge.
trise<='0';
hold = 1;
end if;
end process;
2 Replies
Altera_Forum--- Quote Start --- Try this: always @(Timer) begin if (Timer) begin trise = 1; start = 1; end else begin trise = 0; hold = 1; end end Of course, this is not synthesizable but should work in simulation. Regards, Harald --- Quote End --- Thanx, Harald, it seems better than what I think! :)- Altera_Forum
Try this:
always @(Timer) begin if (Timer) begin trise = 1; start = 1; end else begin trise = 0; hold = 1; end end Of course, this is not synthesizable but should work in simulation. Regards, Harald
