Forum Discussion
FVanE1
New Contributor
New ContributorHow can I connect an IO-PLL output clock to a reference clock input of a transceiver?
I have a ref clock of 312.5 MHz as input at the FPGA, a transceiver which requires 322.265625 MHz and 5.15625 GHz as reference clock inputs. The 5.15625 GHz can I make with a fPLL or ATX-PLL and conn...
SreekumarR_G_Intel
Frequent Contributor
Frequent ContributorHello Frank ,
Sorry i didnt check with you the quartus version to be use before I start and yes I used 19.3 pro version.
If iam not mistaken , i dont think so we have backward compatibilityoptions in quartus.
Anyway i will change the design to 19.2 pro and attach it
Thank you ,
Regards,
Sree
