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FVanE1's avatar
FVanE1
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6 years ago

How can I connect an IO-PLL output clock to a reference clock input of a transceiver?

I have a ref clock of 312.5 MHz as input at the FPGA, a transceiver which requires 322.265625 MHz and 5.15625 GHz as reference clock inputs. The 5.15625 GHz can I make with a fPLL or ATX-PLL and conn...
SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Which IP and device part number you are using ? So I can try it out and create one example design and send to you.

Thank you ,

Regards,

Sree

  • FVanE1's avatar
    FVanE1
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    6 years ago

    Dear Sree,

    I am using the Arria 10 (10AS027E4F29E3SG) as device part and the IP I am using is the "1G/10GbE and 10GBASE-KR PHY Intel Arria 10" (where the 1 GbE interface is disabled). I want to use it in combination with the "Low Latency Ethernet 10G MAC". I also use the "Transceiver PHY Reset Controller".

    Best regards,

    Frank