Forum Discussion

New Contributor

6 years ago

Hold time violations in ALTLVDS_RX with 300 MHz input clock

We are using ALTLVDS_RX to receive high-speed serial data in our design. We have been successfully using this design with 400 MHz input clock (800 Mbps) for a while. We are now trying to use the sam...

altlvds_rx.7z5 KB

KennyT_altera

Super Contributor

6 years ago

Hi Simon,

I just back from Chinese New year,

I had look into your design, firstly, your design are just LVDS without any other logic. The constrain might be inappropriate.

Secondly, you can look into https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/solutions/rd10232012_61.html

Thanks

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Hold time violations in ALTLVDS_RX with 300 MHz input clock

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