Hold time violations in ALTLVDS_RX with 300 MHz input clock

Hi Simon,

I just back from Chinese New year,

I had look into your design, firstly, your design are just LVDS without any other logic. The constrain might be inappropriate.

Secondly, you can look into https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/solutions/rd10232012_61.html

Thanks