Forum Discussion
Altera_Forum
Honored Contributor
8 years agohold time violation using MAX V
Hi,
I saw some hold time violation when I trying to run the STA. I believe the problem is because the source and destination FFs of this path are on different clock domains, and the tool thinks there is large skew between these domains. skew= 5.42, data delay = 3.17, the slack is around -2.3. so is there anything I can do to fix this problem? Thanks!!!!12 Replies
- Altera_Forum
Honored Contributor
For future reference: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/mnl_timequest_cookbook.pdf
Pages 1~8 for clock generation references, pages 3~4 particular for divide-by-N clocks using registers. - Altera_Forum
Honored Contributor
Hi guys,
Thanks a lot of for your help, the problem was fixed!!!