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Yes, unless Quartus detects that FF output as a clock (from your description of the problem however it appears not to).
I would use something like:
create_generated_clock -name two_clkout -multiply_by 2 -source [get_ports {clk}] [get_registers {two_clkout}] and then validate in your DESIGN.sta.rpt file in the CLOCKs table that it appears as it is supposed to as a clock.
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Thanks!!
BUt when I put the clock create_generated_clock, the Quartus tool shows two clocks, one is the output clock (two_clkout) another one is two_clkout~reg0, and it ask me to constrain the two_clkout~reg0.
when I do the RTL simulation, the two_clkout is generated right after the reset signal.
When I do the gate level simulation, the two_clkout is delayed by one input clock cycle.
I'm not sure why it happens.
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