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Hi ak6dn,
Thanks so much for your help!
I just use a FF as a divider, i'm not using the pll to create the output clock, please see below verilog code.
always @(posedge clk or negedge reset)
begin
if (!reset)
two_clkout <= 0;
else
two_clkout <= ~two_clkout;
end
and
sdc comment:
create_clock -name {clk} -period 50.000 -waveform { 0.000 25.000 } [get_ports {clk}]
do I need to put the create_generated_clock for the output clock into the sdc file,even though I just use a FF divider?
Thanks a lot!
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Yes, unless Quartus detects that FF output as a clock (from your description of the problem however it appears not to).
I would use something like:
create_generated_clock -name two_clkout -multiply_by 2 -source [get_ports {clk}] [get_registers {two_clkout}] and then validate in your DESIGN.sta.rpt file in the CLOCKs table that it appears as it is supposed to as a clock.
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