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So output clock is input clock divided by two. Do you use a PLL to generate the output clock, or just a FF as a divider?
Do you use sdc commands
create_clock and / or
create_generated_clock, or
derive_pll_clocks (if using pll). Can you show the sdc commands you use?
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Hi ak6dn,
Thanks so much for your help!
I just use a FF as a divider, i'm not using the pll to create the output clock, please see below verilog code.
always @(posedge clk or negedge reset)
begin
if (!reset)
two_clkout <= 0;
else
two_clkout <= ~two_clkout;
end
and
sdc comment:
create_clock -name {clk} -period 50.000 -waveform { 0.000 25.000 } [get_ports {clk}]
do I need to put the create_generated_clock for the output clock into the sdc file,even though I just use a FF divider?
Thanks a lot!
Honored Contributor
