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Hi,
the output clock is half frequency of input clock. output clock(100ns), input clock(50ns).
when I run RTL simulation, everything looks good.
however, when I trying to run gate level simulation, the output clock always delay one input clock period .
I have set multicycle exception for these two clock, but still see the shift.
set_multicycle_path 1 -setup -start -from CLK -to CLK2
set_multicycle_path 0 -hold -start -from CLK -to CLK2
I not sure what the problem is.
Thanks!
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So output clock is input clock divided by two. Do you use a PLL to generate the output clock, or just a FF as a divider?
Do you use sdc commands
create_clock and / or
create_generated_clock, or
derive_pll_clocks (if using pll). Can you show the sdc commands you use?
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