hold time violation using MAX V

Hi,

the output clock is half frequency of input clock. output clock(100ns), input clock(50ns).

when I run RTL simulation, everything looks good.

however, when I trying to run gate level simulation, the output clock always shift half clock period to the left.

I have set multicycle exception for these two clock,the output clock always delay one input clock period .

set_multicycle_path 1 -setup -start -from CLK -to CLK2

set_multicycle_path 0 -hold -start -from CLK -to CLK2

I not sure what the problem is.

Thanks!