Hold time violation from PLL

Question

Hi ,

My input clock is 50 Mhz and i am using PLL to generate 6 Mhz (Stratix III) . But i am getting violation e.g

How can i resolve this violation ?

currently constaint is specified like this

create_generated_clock -name {FPGA_PLL_INST|altpll_component|auto_generated|pll1|clk[0]} -source [get_pins {FPGA_PLL_INST|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 3 -divide_by 25 -master_clock {i_osci_clk} [get_pins {FPGA_PLL_INST|altpll_component|auto_generated|pll1|clk[0]}]

altera_forum · Answer

Are you sure you are not gating the 6MHz clock?

altera_forum · Answer

i am gettign 6 Mhz clock , but there are some violations on the ARM core , i am using ARM core (core_m28, Vhdl code ) in my desing and 6 Mhz clock goes to the ARM core , where i see the violation .

e.g

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Hold time violation from PLL

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