Hold time violation from PLL

i am gettign 6 Mhz clock , but there are some violations on the ARM core , i am using ARM core (core_m28, Vhdl code ) in my desing and 6 Mhz clock goes to the ARM core , where i see the violation .

e.g

0.854 core_m28:CORE_INST|mem_bank:mem_bank_INST|ev_fifo_ rd_data_d[6] core_m28:CORE_INST|ICN1:Interconnect_system_INST|G enericConv_5_c6sb0_genconv_top:GenericConv_5|Gener icConv_5_c6sb0_tconv_3to1:c6sb0_tconv_3to1_0|t3_r_ data_reg[1][6] FPGA_PLL_INST|altpll_component|auto_generated|pll1 |clk[0] FPGA_PLL_INST|altpll_component|auto_generated|pll1 |clk[0] 0.000 2.659 1.865