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Altera_Forum
Honored Contributor
Honored ContributorHold time violation from PLL
Hi , My input clock is 50 Mhz and i am using PLL to generate 6 Mhz (Stratix III) . But i am getting violation e.g ...
Altera_ForumHonored Contributor
Honored ContributorAre you sure you are not gating the 6MHz clock?
