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... it is not unusual to get hold violations between registers in two different kinds of resource blocks (LAB, RAM block, DSP block, I/O cell).
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It's unusual for Quartus not to get this right.
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I should have been more clear. I meant that this kind of hold violation is not unusual when the Fitter is not optimizing hold for all paths. I don't recall ever seeing this kind of hold violation when I did enable this hold optimization including fast-corner optimization.
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I usually find that the reason for hold errors is that the clock path delay is much larger than I thought - typically because someone created a gated clock...
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What drdr6 suggested for gated clocks is good advice for the Classic Timing Analyzer. For either timing analyzer, look for unusually large clock skew. In TimeQuest you can look through details of the clock paths for the source and destination registers if you use "-detail full_path" for report_timing; that is similar to looking through the Classic Timing Analyzer List Paths submessages as drdr6 suggested. For Report Timing in the TimeQuest GUI, you can see the clock skew on the "Statistics" tab.
If you do have a gated clock, then see
http://www.alteraforum.com/forum/showthread.php?t=2388.
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... go "list paths"
In the box at the foot of the screen, open all the little boxes with + in them...
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To open all the List Paths submessages at once, press <Ctrl> while clicking the "+".
Honored Contributor
