Hold errors

It's unusual for Quartus not to get this right.

I usually find that the reason for hold errors is that the clock path delay is much larger than I thought - typically because someone created a gated clock.

Find the hold error in the timing analyzer and then right click on it and go "list paths"

In the box at the foot of the screen, open all the little boxes with + in them until you can see the path of the clock for your second register bank. Check it isn't going somewhere you didn't expect, like not on a global wire, or through an LAB.