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I'm getting a hold error...
I do have the 'all paths' turned on.
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If the hold violations are only with the fast timing model, then did you also turn on "Optimize fast-corner timing"?
Even if you already are using global routing as pletz suggested, it is not unusual to get hold violations between registers in two different kinds of resource blocks (LAB, RAM block, DSP block, I/O cell). The routing hop between the global metal and the register inside the block has different delays for these different blocks, causing some clock skew. I haven't had any trouble fixing these hold violations with the Fitter's hold optimization. I don't remember seeing hold violations between registers in the same kind of resource block when using global routing for the clock, but it is possible to have some small clock skew even in that case.
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