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cosx's avatar
cosx
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

HLS compiled qsys modification and regeneration problem

Hi everone,

I came across a question about modifying HLS generated qsys and regeneration of the modified system.

My quartus SDK compiler is 15.1.

I compiled a .cl file using command "aoc -s -v ().cl --board (board_name)".

A qsys named system.qsys had been generated. Next I modified this system by adding some customised components.

After saving ths system, I regenerated this system.qsys into .v file. The command I used for regenerate was

'qsys-generate system.qsys --synthesis=VERILOG --family="CYCLONE V" --simulation=VERILOG'.
After doing this, however, the system.v was not shown in the synthesis folder. Nor was it shown in simulation folder.
Before regeneration, I had already removed all HLS generated system folder and "system.tcl" file. However, the system.v was still not there.
May I ask if the .v file has been hidden or something else happened?
I have also attached the whole project for your references.
Thank you very much!
Mingqiang

3 Replies

  • cosx's avatar
    cosx
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hi everyone,

    A new update here:

    when I use aoc -v to compile the project, some strange messages occur:

    com.altera.hdlwriter.EntityWritingException: Connection is not connected float_add:avm_local_bb1_ld__inst0 -> ?
    at com.altera.hdlwriter.internal.OldEntityWriterInternal.addConnection(OldEntityWriterInternal.java:431)
    at com.altera.hdlwriter.internal.OldEntityWriterInternal.writeHDLInternal(OldEntityWriterInternal.java:122)
    at com.altera.hdlwriter.internal.EntityWriter.writeHDL(EntityWriter.java:40)
    at com.altera.sopc.generator.EnsembleGenerationFileSet2.generate(EnsembleGenerationFileSet2.java:61)
    at com.altera.sopc.generator.FileSet2.generate(FileSet2.java:150)
    at com.altera.sopc.generator.Sellafield.generate(Sellafield.java:366)
    at com.altera.sopcmodel.sbtools.sbgenerate.SbGenerate.performGeneration(SbGenerate.java:518)
    at com.altera.sopcmodel.sbtools.sbgenerate.SbGenerate.act(SbGenerate.java:464)
    at com.altera.utilities.AltCmdLineToolBase.runTheTool(AltCmdLineToolBase.java:718)
    at com.altera.sopcmodel.sbtools.sbgenerate.SbGenerate.main(SbGenerate.java:965)
    May I ask has anyone come across this before?
    It seems that my defined IP has problems, but don't know why it has problems..
    Thank you again!
    Mingqiang
    • OliverTheEngineer's avatar
      OliverTheEngineer
      Icon for New Contributor rankNew Contributor
      1 year ago

      Hello Cosx,

      I'm having exactly the same problem, 4 years later... I have not seen any other occurrences of this error, do you remember if and how you solved it?

      Thank you,

      Oliver

  • OliverTheEngineer's avatar
    OliverTheEngineer
    Icon for New Contributor rankNew Contributor
    1 year ago

    It turns out that this error is due to a mistake in the signals on Platform Designer. In my case, I had chosen the wrong size for my APB PSEL signal. I found out by creating an example component with a template APB interface and observing the given signals.