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Altera_Forum
Honored Contributor
Honored ContributorHigh Level, Low Level, stratix II.
I have a data signal with low voltage peak to peak (only 0.5 volts). I want my stratix II FPGA to understand it as a zero and one. To do that I tried changing my input from 3.3v to 1.5, but qu...
Altera_ForumHonored Contributor
Honored Contributoryou can also try using differential signaling, with one side stuck at 0.5V and the other one being your signal
