NShan12
Occasional Contributor
Occasional ContributorHierarchy not retained in Modelsim during RTL simulation
Hello,
I am using QP 20.1.1 STD.
I have a hierarchical design (comprising VHDL and BDF flies), see screenshot (some names hidden):
When I launch RTL Simulation from Quartus, I see that ...
Naveen,
Seem like the other instance is not in Modelsim is due to unsupported format for Modelsim, you have to convert to HDl in order to simulate it.
https://www.intel.com/content/www/us/en/support/programmable/articles/000078436.html
