Hi. Should i re-bias the ARRIA10 REFCLK receivers after AC coupling? this is specifically meant for HCSL.

I'm designing a Mother Board that includes a PCIe connection to several ARRIA10 devices. The PCIe standard includes a 100 Mhz REF CLK .

I'm using CLK synthesizer (ZL30267 Microsemi) to distribute the PC (root) CLK to all other devices (eight FPGAs). one on board, seven other connected via connectors.

Between the ZL30267 driver and all other FPGAs receivers, i'm biasing the driver output (i'm driving HCSL CLK) and using AC coupling.