Forum Discussion
4 Replies
- AnandRaj_S_Intel
Regular Contributor
HI,
- Did you test .sof file programming via JTAG configuration, Is it successful?
- If the .sof file can be configure via JTAG successfully then it is not a power issue since JTAG configuration is successful.
- If the JTAG configuration with .sof file failed, thus it is a power issue need to check the POR.
You can can check the FPGA device POR monitored power supplied if those power supply are ramped up to the appropriate voltage level according to the device datasheet and are stable throughout the operation. The nSTATUS is only release to high when the FPGA device POR monitored power supplied are power up correctly.
Let me know if this has helped resolve the issue you are facing or if you need any further assistance.
Best Regards,
Anand Raj Shankar
(This message was posted on behalf of Intel Corporation)
- mstef1
New Contributor
hI,
Thank you for your answer,
the 1.2 and 2.5V voltages are rise fastly, the vccio (3.3v) is rising within 2mS.
where I can check the POR timing in quartus?
I am not working with JTAG (because I have the AS programmer only, byte bluster II), then the config time will depend by EPCS64 (this is what I understood).
have you any other suggestions?
thank you
maurizio
- mstef1
New Contributor
HI,
again I checked the nSTATUS signal with and without pull-up resistor. the signal remains "low".
I checked the power voltages and they are ok.
the 1.2 and 2.5V rise fastly, the 3.3V .
please find attached the 3.3V power-up sequence
maurizio
- AnandRaj_S_Intel
Regular Contributor
HI,
Check the Recommended Operating Conditions tables
Best Regards,
Anand Raj Shankar
(This message was posted on behalf of Intel Corporation)