Helpless about "GE 1588 V2 1PPS SYNC "

HI Mark,

Sorry, pls ignore my suggestion on the TOD sync IP - sync mode setting.

I clarified further with Intel internal team.

• The TOD sync IP is just good to sync up the master TOD and slave TOD IP within the FPGA internally.
• It won't help to sync the offset between PTP slave device (FPGA) and PTP master device (your test equipment)

Ultimately user is still expected to build your own design algorithm to adjust the PTP offset btw master and slave device yourself. From Intel FPGA Ethernet IP side, we only provide the timestamp info but not the offset adjustment solution

I dig through some reference design and found below example design that comes with PTP offset adjustment software stack solution.

• https://rocketboards.org/foswiki/Projects/Stratix10SoCDesignExampleFor10GbeWithIEEE1588PTPCapability
• I am not sure how helpful is it but feel free to check it out

Thanks.

Regards,

dlim