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mark_lee's avatar
mark_lee
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Helpless about "GE 1588 V2 1PPS SYNC "

Hi team I had debug GE 1588 V2 in my board is Slave , and Third party equipment is Master。The 1PPS signal output from my board is sync to the 1PPS signal output from the Master equipmen...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi Mark,


I am afraid we won't be able to provide assistance to you on the offset adjustment.


This is due to Intel FPGA IP does not implement event messaging protocol layer, but only provide basic hardware capability (i.e. timestamping) in implementing 1588 protocol


User logic will manage PTP messaging and corresponding offset adjustments. My understanding is the offset algorithm is typically managed by high level software stack.


Another suggestion to you is perhaps you can check back with your test equipment vendor to see if they are able to provide you further guidance or any setting that can fine tune in the test equipment or not.


Thanks.


Regards,

dlim