Helpless about "GE 1588 V2 1PPS SYNC "

hello anybody

Did I put the post in the wrong board?

Hi Mark,

I am afraid we won't be able to provide assistance to you on the offset adjustment.

This is due to Intel FPGA IP does not implement event messaging protocol layer, but only provide basic hardware capability (i.e. timestamping) in implementing 1588 protocol

User logic will manage PTP messaging and corresponding offset adjustments. My understanding is the offset algorithm is typically managed by high level software stack.

Another suggestion to you is perhaps you can check back with your test equipment vendor to see if they are able to provide you further guidance or any setting that can fine tune in the test equipment or not.

Thanks.

Regards,

dlim

Another suggestion is you can also try play around with the sync mode of the "TOD sync IP" page 13, table 14

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20019.pdf

HI Mark,

Sorry, pls ignore my suggestion on the TOD sync IP - sync mode setting.

I clarified further with Intel internal team.

• The TOD sync IP is just good to sync up the master TOD and slave TOD IP within the FPGA internally.
• It won't help to sync the offset between PTP slave device (FPGA) and PTP master device (your test equipment)

Ultimately user is still expected to build your own design algorithm to adjust the PTP offset btw master and slave device yourself. From Intel FPGA Ethernet IP side, we only provide the timestamp info but not the offset adjustment solution

I dig through some reference design and found below example design that comes with PTP offset adjustment software stack solution.

• https://rocketboards.org/foswiki/Projects/Stratix10SoCDesignExampleFor10GbeWithIEEE1588PTPCapability
• I am not sure how helpful is it but feel free to check it out

Thanks.

Regards,

dlim

Hi Deshi

Thank you for your help and support about the 1588 PTP

Thanks.

Regards,

mark