Help with RS232 module

Well you should check your PLL output clock (for 9600 baud, for example) out one of your user accessible pins and look at it on a scope to confirm it is exactly the frequency that you want. I suggest doing the same for your system clock as well. Also you might also (for a receive unit on your fpga) introduce in the same PLL block a clock out that is a multiple (something large, maybe 16times (9600*16 = 153600Hz) or 32 times (or even more) your 9600 Hz) for sampling the incoming rx signal at the middle of the "ideal" bits. That way you should get very low bit error rates because of asynchronous clocks. In a sense rs232 is self timing due to the timing being based on a start bit. Eventually you'll probably want to come up with your own checksuming or CRC, depending on your system and it's ability to handle faulty data.