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Altera_Forum's avatar
Altera_Forum
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11 years ago

Help with making an osciloscope on NIOS II

Good day every one!

I would like to make a simple 6 channel, 250 kSa oscilloscope using NIOS II/f.

I am using DE0-NANO (Cyclone IV, 32 MB SDRAM) and I already have device built (6 channel ADC connected to SDRAM, pushbuttons, graphical LCD, some batteries).

Now main problem:

I wrote driver for my ADC and DATA is extracted by parallel ports.

My first attempt was to write data from 6 PIO to SDRAM using CPU (but as you can guess, this task was killing any other IRQ).

Later I was trying using DMA, SGDMA and mSGDMA to copy data from PIO to SDRAM, but without any success (I have spend so many hours on this... :evil: I hate myself).

What I would like to ask you is to help me find best way getting this data (10 000 samples per channel) into SDRAM.

Please help me with this matter, any guide will do.

Best Regards

Michael

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    I'd use a FIFO buffer between the PIOs and the sdram.

    The PIOs needs to be read exactly at the 250ks x 6 rate , otherwise you'll lose data.

    I'm concerned dma+sdram can allow such a regular access, especially if sdram is being accessed by other devices.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    I would go as far as saying create your own component to interface with the ADC that writes to the FIFO and then connect any of the DMA blocks you care to use to the read side of the FIFO.

    If you want to get there with only off the shelf blocks and are less concerned with resource utilization, as Cris72 mentioned, you probably want something like (PIO->DMA1->DCFIFO->DMA2->SDRAM). DMA1 runs at your sampling rate. DMA2 runs at SDRAM interface frequency.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Is there any easy way to write externally DATA into SDRAM? or on_chip_ram?

    I thought DMA should be used for this, but DMA can only access internal (maybe export ports?) registers.

    Also could you provide more information about making this connection PIO->DMA1->DCFIFO->DMA2->SDRAM?
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    Is there any easy way to write externally DATA into SDRAM? or on_chip_ram?

    I thought DMA should be used for this, but DMA can only access internal (maybe export ports?) registers.

    --- Quote End ---

    Using DMA is the easiest way.

    --- Quote Start ---

    Also could you provide more information about making this connection PIO->DMA1->DCFIFO->DMA2->SDRAM?

    --- Quote End ---

    The above sequence of blocks is basically what you said you already had, except it adds another DMA and a FIFO. The first DMA reads from the PIO and writes into the FIFO. The second DMA reads from the FIFO and writes to SDRAM. The FIFO needs to be deep enough to accomodate any backpressure from the SDRAM due to refresh or other accesses.

    If you still aren't sure how to possibly proceed, maybe post your project?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    Is there any easy way to write externally DATA into SDRAM? or on_chip_ram?

    I thought DMA should be used for this, but DMA can only access internal (maybe export ports?) registers.

    --- Quote End ---

    DMA can be indeed used for this.

    The problem, as I stated before, is that sdram can't ensure the required throughput.

    One reason is strictly connected with physical sdram access mode, which is not a simple rw/rd with a deterministic access time like sram: latencies due to row and column selection are involved; row precharge and possibly a refresh cycle can further delay the transaction.

    The second reason is that sdram is usually shared with other devices, so the dma transfer can be delayed because someone else is accessing sdram when you need it.

    That's why you need a dedicated buffer or fifo to store adc data at fast rate.