Forum Discussion
Altera_Forum
Honored Contributor
15 years agoHelp with HIL
I have a Stratix III EP3SL150F1152C2 FPGA. My aim is to put the "demo_fft256_radix4" example provided by the DSP builder in the FPGA and run it to solely demonstrate high speed simulations that can b...
Altera_Forum
Honored Contributor
15 years agoThanks for replying. I am not able to pot the .mdl file due to size constraints. I am attaching the screenshots of my model and the error I get. What I also don't understand is how can I generate the ports for the HIL block. Right now my HIL block is just sitting on the DUT block. I want to replace that with HIL for which the HIL block needs to have it own ports. I went through the user guide couple of times and still couldn't figure out how to go about. If you could help me with these two issues (fixing the error and generating ports for HIL block) it would be really helpful.
https://www.alteraforum.com/forum/attachment.php?attachmentid=3429 https://www.alteraforum.com/forum/attachment.php?attachmentid=3430 https://www.alteraforum.com/forum/attachment.php?attachmentid=3431 https://www.alteraforum.com/forum/attachment.php?attachmentid=3432