Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Help with CIC decimation filter

Hi, I wrote a Verilog code for a CIC decimation filter. I relied on a code written in the book 'digital signal processing with FPGA' . Here is the code: // cic decimation filter : R=64, M...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

You should be able to trace the x state from the assignment:

i0 <= i0+sx;

and

assign sx={{16{x[7]}},x_in};

surely it must be either sx or x_in or x entering x state

edit: or i0 first value is x state