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Honored Contributor
Honored ContributorHelp with CIC decimation filter
Hi, I wrote a Verilog code for a CIC decimation filter. I relied on a code written in the book 'digital signal processing with FPGA' . Here is the code: // cic decimation filter : R=64, M...
Altera_ForumHonored Contributor
Honored ContributorIt could be because the very first value on input x is x so you need to initilise x just like your clock.
