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Altera_Forum's avatar
Altera_Forum
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14 years ago

help with altpll megafunction.

I used the Megawizard plug-in manager to create the altpll megafunction. The altpll files are included in my project and I added it as a component in my code:

(this is part of the code)

component altpll0

port (sys_clk: IN STD_LOGIC;

nclk: OUT STD_LOGIC);

end component;

BEGIN

pll0: altpll0

port map (sys_clk => sys_clk, nclk => nclk);

I am new to VHDL so I don't know if I'm doing this right or if this is the wrong way to include the megafunction.

I get these errors when I compile:

Error (10309): VHDL Interface Declaration error in hw3.vhd(79): interface object "nclk" of mode out cannot be read. Change object mode to buffer.

Error (10577): VHDL error at hw3.vhd(79): actual port "nclk" of mode "out" cannot be associated with formal port "clock0" of mode "in"

Error (10600): VHDL error at hw3.vhd(79): can't read value of interface object "nclk" of mode OUT

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    I recommend to use *.bdf file as top-level entity in your project.

    This visual approach is convenient because you can represent all your own VHDL-modules and megafunctions created by megawizards as symbol modules in top-level entity.

    So, it won't be necessary to deal with code generated by ALTPLL megawizard.

    You need to configure your ALTPLL instance in megawizard properly and then connect I/O ports of ALTPLL with other ports of symbol modules in top-level entity.

    P.S. To create symbol of your VHDL-module select "File -> Create/Update -> Create Symbol Files for Current File".

    Then you can insert your symbol in top-level entity by "Symbol Tool" button.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    frostyourself,

    you can't use arbitrary names for the module's ports; you need to use the same names which are in the module generated by the megawizzard.

    So, you need to correct your component declaration and the module instantiation to something like.

    component altpll0

    port (inclk0 : in std_logic; c0: out std_logic)

    end component;

    pll0 : altpll0 port map( inclk0 => sys_clk, c0 => nclk);