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Altera_Forum
Honored Contributor
14 years agofrostyourself,
you can't use arbitrary names for the module's ports; you need to use the same names which are in the module generated by the megawizzard. So, you need to correct your component declaration and the module instantiation to something like. component altpll0 port (inclk0 : in std_logic; c0: out std_logic) end component; pll0 : altpll0 port map( inclk0 => sys_clk, c0 => nclk);