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Altera_Forum's avatar
Altera_Forum
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14 years ago

help with 1 to 8 Demux

Hi all,

I am tried to write VHDL code for 1 to 8 Demux and that's what i finish with it

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

use ieee.std_logic_unsigned.all;

ENTITY Dmux1to8 IS

PORT ( X : IN STD_LOGIC;

S : IN STD_LOGIC_VECTOR(0 TO 2);

En : IN STD_LOGIC;

W : OUT STD_LOGIC_VECTOR(0 TO 7));

END Dmux1to2;

ARCHITECTURE Structure OF Dmux1to8 IS

SIGNAL m : STD_LOGIC_VECTOR(0 TO 5);

BEGIN

G1: FOR i IN 0 TO 1 GENERATE

Dec_ri: Demux1to2 PORT MAP ( m(i), S(0), X);

G2: FOR i IN 2 TO 5 GENERATE

Dec_left: Demux1to2 PORT MAP ( m(i), S(1));

END GENERATE ;

END GENERATE ;

Demux5: Demux1 to 8 PORT MAP ( m(2),m(3),m(4),m(5), S(2), W(0 TO

7) );

END Structure;

can any one told me if is it right or not?

if there are any mistakes can you help me to correct it ?

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    There are mistakes.

    Try and compile it and you'll get an error report.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    what are the mistakes ?

    i can't because the programme is not working with me :(
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Like I said on EDA board, there are plenty of errors.

    its not going to work, because

    1. you havent included any libraries for the demuxes to be taken from.

    2. Without the library, there is no component declarations.

    3. In demux 5, you cannot have spaces in the name.

    I have no idea if its going to work even when the above are fixed, becaise you havent included the code for the demuxes.

    Why didnt you try and run it throguh a compiler instead of just pasting code in a post?

    Now it seems a new error is no compiler.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Did you mean "Selector"?

    if this is the case, why should you insert by GENERATE statement?

    If the following signals:

    inputs : std_logic_vector (7 downto 0);

    select : std_logic_vector (2 downto 0);

    output : std_logic;

    Then just write the following combinatorial code:

    output <= input (to_integer(unsigned(select)));

    the "unsigned" function tells VHDL to threat the "select" bus as UNSIGNED, with no negative numbers interpretation.

    the "to_integer" function converts the "select" bus to integer value so i may be used for indexing the "inputs" array.

    don't forget to add the libraries, like these ones:

    use ieee.std_logic_unsigned.all;

    use ieee.numeric_std.to_integer;
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    i can't because the programme is not working with me :(

    --- Quote End ---

    I suggest you fix this problem first then.