help with 1 to 8 Demux

Did you mean "Selector"?

if this is the case, why should you insert by GENERATE statement?

If the following signals:

inputs : std_logic_vector (7 downto 0);

select : std_logic_vector (2 downto 0);

output : std_logic;

Then just write the following combinatorial code:

output <= input (to_integer(unsigned(select)));

the "unsigned" function tells VHDL to threat the "select" bus as UNSIGNED, with no negative numbers interpretation.

the "to_integer" function converts the "select" bus to integer value so i may be used for indexing the "inputs" array.

don't forget to add the libraries, like these ones:

use ieee.std_logic_unsigned.all;

use ieee.numeric_std.to_integer;