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Altera_Forum
Honored Contributor
11 years ago --- Quote Start --- That makes sense so I'm good now. --- Quote End --- Great! --- Quote Start --- I'll change over to setting the bust to 'Z' when I have a 1 to send over the I2C bus from the slave. This was a great help and really cleared this up for me! --- Quote End --- You can easily make the change at the top-level of your design. Lets say your outputs are scl_out and sda_out, then the tri-state/low drivers in VHDL are;
scl <= 'Z' when (scl_out = '1') else '0';
sda <= 'Z' when (sda_out = '1') else '0';
Cheers, Dave