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Occasional ContributorHelp on understanding Agilex5 speed binning and static power
Agilex 5 parts have high static power by industry traditions, so using Agilex in our designs needs some attention.
Using the PTA 26.1.110: fixed junction temperature
Is there going to be facility in the PTA to vary the core power supply values over the min and max range ? via tcl ?
Will there be a model update soon? most of the values I get seem same for ES and production silicon in the PTA.
(static power , 50 deg C, typical ) power of 100 DSPs at 200 MHz, + LPDDR4(32 + usage defaults)
A5EE008BB23BE6X : 551mW , + 200mW, +576 mW
A5EE008BB23BE6S : 759mW, +200mW , +576mW
A5EE008BB23BE5S : 666mW, +216 mW, +592mW
A5EE008BB23BE4S : 739mW , +227mW, +604mW
sweet spot speed/static/cost appears to be -5
notes : Static power is 2x Xilinx ZU2CG....
Turning on all those I/Os for the EMIF LPDDR4 hurts alot for Agilex5. ALthough the defaults for EMIF write/read and toggle rates are high (50%) so, might be pessimistic.
But, the DSPs consume about half what XIlinx Ultrascale+ does....
FWIW Xilinx Ultrascale+ DSP consumption is 560mW (25x18) for same task. So Agilex wins there .
(but Ultrascale+ can operate much faster -1 xilinx (slowest) = -2V Agilex (fast)) .
Agilex 5 static and I/O power is massively higher, but when it gets busy, Agilex 5 fabric functions are lower power cost than Ultrascale+. Agilex5 may not be the best choice for battery operated devices... Agilex 5 is best when it is busy and heavily utilized, only then it has power advantages over Ultrascale+
Glen
2 Replies
AqidAyman_AlteraRegular Contributor
Hi Glen,
PTA does support Tcl automation (quartus_pta -t <script.tcl>). Public PTA scripting docs cover device selection, resource entry, and results. However, I do not find a documented Tcl parameter that sweeps fabric core VCC across a SmartVID min/max range. See the Power and Thermal Analyzer User Guide, "Running Scripts with the Power and Thermal Analyzer": https://docs.altera.com/r/docs/865226/26.1/power-and-thermal-analyzer-user-guide/running-scripts-with-the-power-and-thermal-analyzer
PTA uses a device power model whose maturity is shown as advance, preliminary, or final in Device Selection. Matching ES and production estimates usually means those OPNs are on the same model maturity today. Check the model status for each part in PTA. For competitive or BOM work, the ES errata also recommend using production OPNs when you can.
Your four OPNs are fixed-voltage grades (S / X), not SmartVID (V / E). Static differences are expected to track the fixed core supply for that grade. Pin Connection Guidelines require sharing VCCL_HPS with VCC. For VCCL_SDM (same grade voltage family on these fixed parts): -4S at 0.8 V, -5S at 0.78 V, -6S and -6X at 0.75 V. See Pin Connection Guidelines: Agilex 5 FPGAs and SoCs: https://docs.altera.com/r/docs/813266/current
That lines up with your PTA ranking: -6X lowest static, then -5S, then -4S / -6S higher. Same nominal voltage on -6X vs -6S with lower -6X static is consistent with X being the lowest-voltage / low-power fixed option; PTA models that grade differently from S.
On your -5S "sweet spot" and regulator sizing for ES silicon: for Agilex 5 ES, Altera requires multiplying the dynamic current on each rail from the Power and Thermal Calculator / PTA by 1.2 when sizing the voltage regulator. Apply that if the BOM is still based on ES. Refer to Agilex 5 ES Device Errata and User Guidelines, Power Estimation Guardband: https://docs.altera.com/r/docs/825514/current
Your broader read is fair for these fixed-voltage grades: higher static / I/O floor, stronger when the fabric (especially DSP) is busy. SmartVID grades (-1V / -2V / -2E / -3V) are the ones that can pull static down through VID adaptation.
Regards,
Aqid
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