The FPGA refuse to work after I program it! I use two way to program my design, one is programming to EPC16 which is connect to FPGA, another is programming to FPGA directly. but FPGA has no reaction after programming,although the process is going on sucessfuly to 100%. this problem comes suddenly, as this FPGA work correctly before.any one who once met this problem ,give me help ,thanks!

--- Quote Start --- The FPGA refuse to work after I program it! I use two way to program my design, one is programming to EPC16 which is connect to FPGA, another is programming to FPGA directly. but FPGA has no reaction after programming,although the process is going on sucessfuly to 100%. this problem comes suddenly, as this FPGA work correctly before.any one who once met this problem ,give me help ,thanks! --- Quote End --- Hi, are you using a new programming file or an old one which runs before ? Kind regards Gerd

Have you tried measuring the clocks, pll lock signals and resets? Another thing can be to program something else into the fpga. Some simple design that toggles pins or something like that just to see if the FPGA or the design is the problem. Best Regards, Ola Bångdahl (trying to avoid doing actual work...)

Thank you for your reply , I use an old one, the same one as I use before!

--- Quote Start --- Have you tried measuring the clocks, pll lock signals and resets? Another thing can be to program something else into the fpga. Some simple design that toggles pins or something like that just to see if the FPGA or the design is the problem. Best Regards, Ola Bångdahl (trying to avoid doing actual work...) --- Quote End --- Thank you for your reply. May be ,I see. I'm try to check whether the crystalloid is OK.

help ON EP2S60 FPGA | Altera Community

13 Replies

Altera_Forum
Honored Contributor
16 years ago
--- Quote Start ---
I am using the USB byte blaster rev B.

Before I do a Erase action the Quartus (9.0) and do auto detect the chain is seen correct. Both with the USB blaster and the Jtag Technologies hard/software.

Now starts the problem : after I do a "erase" with quartus and do a power dwn up again there's no chain seen with both tools (JT and USB blaster).
The TDO is only high ( it looks like high Z).

Hans
--- Quote End ---

Hi Hans,

is it possible for you to change the JTAG Chain, so that only your Stratix Devcie is in the Chain ?

Kind regards

GPK
Altera_Forum
Honored Contributor
16 years ago
Yes I allready did that, it's a Mezzanine board normally tested in a system.

But also possible to test it seperately.

It's not only the TDO but I think the complete TAP is disappeared after erase with quartus. I tried to put the device in extest but nothing happened.
The only thing I can think of is that the erase action is writing something in the private registers ( see the last lines from the ep2s60 bsdl) :

"The following private instructions must not be used as they"&
"may render the device inoperable:"&
" "&
" 1100010000 "&
" 0011001001 "&
" 0000101001 "&
" 0000010000 "&
" "&
"Customer should take precautions not to invoke these instructions"&
"at any time. Contact Altera Applications for further assistance.";
Altera_Forum
Honored Contributor
16 years ago
--- Quote Start ---
Yes I allready did that, it's a Mezzanine board normally tested in a system.

But also possible to test it seperately.

It's not only the TDO but I think the complete TAP is disappeared after erase with quartus. I tried to put the device in extest but nothing happened.
The only thing I can think of is that the erase action is writing something in the private registers ( see the last lines from the ep2s60 bsdl) :

"The following private instructions must not be used as they"&
"may render the device inoperable:"&
" "&
" 1100010000 "&
" 0011001001 "&
" 0000101001 "&
" 0000010000 "&
" "&
"Customer should take precautions not to invoke these instructions"&
"at any time. Contact Altera Applications for further assistance.";
--- Quote End ---

Hi,

sorry I'm not a JTAG expert. Maybe you should contact the altera Application guy's.

Kind regards

GPK

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help ON EP2S60 FPGA

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