Help needed for this 3 bit parity generator/checker.

:cry: Im a total Noob and seriously need help in my VHDL.

the question:

To design a 3-bit parity generator/checker that has three data inputs (A to C) and two odd/even parity outputs (odd_out and even_out). When the number of high level input is odd, odd_out is kept HIGH and even_out output LOW. Likewise, if the number of high level input is even, even_out is kept HIGH and odd_out LOW. The design of this generator is to be written in VHDL. Produce the truth table for this generator and treat C as the MSB.