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Altera_Forum's avatar
Altera_Forum
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17 years ago

help me to translate verilog to vhdl

hello, is there anyone expert in both verilog and vhdl?? i did learn only vhdl..help me to translate these codes into vhdl.. `timescale 1ns / 1ps module mctrl( input clk, ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Looking at that code, it doesn't seem too complicated and probably if you consult Wikipedia then you'll probably be able to bluff your way through it enough to produce a VHDL replica. Do consider how complicated the underlying blocks are though if you have to translate these as well.

All the advice against doing this is valid and pretty sensible but to add a few points the other way:

If you're relying on a free Modelsim licence then you won't be able to do mixed-language simulation.

If you're including this block in a design then who is supporting it? Are you being expected to support a design in a language you don't understand?

What are your timescales on the projects - if they're not tight then you may well find that re-writing this block in a supportable language and performing plenty of simulation to verify that you've done it right and can support the project long-term, might outweigh the risk of introducing a bug along the way.