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Altera_Forum's avatar
Altera_Forum
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16 years ago

Help in verilog code...

I have given a task of writing a verilog code for moving the stepper motor for desired number of steps in either clock wise or CCW direction . i have written the following code but when i simulate it using model sim , it shows high impedance values for all the ports ... the code is given below ...

======================================================

// PROGRAM BLOCK

module stepper(out ,n_steps, dir_CW);

output reg [3:0]out;

input [7:0]n_steps;

input dir_CW;

integer i;

initial

begin

i <= n_steps;

out <= 4'b0000;

end

always @(n_steps or dir_CW)

begin

if (dir_CW ==0)

begin

while(i>=4)

begin

# 2 out = 4'b1001;

# 2 out = 4'b1010;

# 2 out = 4'b0101;

# 2 out = 4'b0110;

i = i - 4;

end

if (i==3)

begin

# 2 out = 4'b1001;

# 2 out = 4'b1010;

# 2 out = 4'b0101;

end

else if (i==2)

begin

# 2 out = 4'b1001;

# 2 out = 4'b1010;

end

else if (i==1)

begin

# 2 out = 4'b1001;

end

else;

end

else

begin

while(i>=4)

begin

# 2 out = 4'b0110;

# 2 out = 4'b0101;

# 2 out = 4'b1010;

# 2 out = 4'b1001;

i = i - 4;

end

if (i==3)

begin

# 2 out = 4'b0110;

# 2 out = 4'b0101;

# 2 out = 4'b1010;

end

else if (i==2)

begin

# 2 out = 4'b0110;

# 2 out = 4'b0101;

end

else if (i==1)

begin

# 2 out = 4'b0110;

end

else;

end

end

endmodule

// TESTING BLOCK

module test;

reg [7:0]N_STEPS;

reg DIR_CW;

wire [3:0]OUT;

stepper stpr(OUT, N_STEPS, DIR_CW);

initial

begin

$display("no of steps = %b, CW direction = %b, coils output = %b\n", N_STEPS,DIR_CW,OUT);

end

initial

begin

N_STEPS= 8'b0001_0000; DIR_CW= 1'b0;

//# 100 N_STEPS= 8'd80; DIR_CW= 1'b1;

end

endmodule

=======================================================

please anybody help me out in correcting this code if the logic gets wrong as i m new to verilog ...

Regards

Umair

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    This cannot be corrected.

    You need to describe a circuit.

    What you wrote is a code for simulation that does not correspond to a circuit.

    I suggest you to read a Verilog book such as:

    Verilog HDL Synthesis, a practical primer from Bhasker or

    A Verilog HDL primer from the same author.

    Among the most important errors:

    1) initial : is not synthetizable in a circuit

    2) Among the frist line you write i <=n_steps;

    this means : a wire connects the input n_steps and the signal i so they're equal.

    After some line you write i=i-4 ?? If i is connected to n_steps it cannot be equal to itself minus 4.

    Do you want to synthesize a decreasing counter?

    Put a flip-flop where to memorize n_steps once every while.

    Then use the memorized value to drive a counter (made with a register and a sum)
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    thanks alot sir ... bt what i want is to store the value of n_steps (which is the desired no of steps to be driven as user input) in a variable so that i can decrement it once the stepper motors performs a step ... so how do i store the value of input n_steps in a variable (integer) and decrement it as "i = i-4". I am not implementing it on real circuit but just simulate it and i think for simulation i can use initial block ...

    waiting for your reply ...