Help in verilog code...

This cannot be corrected.

You need to describe a circuit.

What you wrote is a code for simulation that does not correspond to a circuit.

I suggest you to read a Verilog book such as:

Verilog HDL Synthesis, a practical primer from Bhasker or

A Verilog HDL primer from the same author.

Among the most important errors:

1) initial : is not synthetizable in a circuit

2) Among the frist line you write i <=n_steps;

this means : a wire connects the input n_steps and the signal i so they're equal.

After some line you write i=i-4 ?? If i is connected to n_steps it cannot be equal to itself minus 4.

Do you want to synthesize a decreasing counter?

Put a flip-flop where to memorize n_steps once every while.

Then use the memorized value to drive a counter (made with a register and a sum)