Forum Discussion
Honored ContributorHelp: HSMC and I2C
I am having a hell of a time trying to interface a camera through an HSMC - Santa Cruz adapter board (THDB-H2S - http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=39&no=219)
On a typical HSMC connector, are the I2C pins electrically different than PIO pins? If so this would indicate that my problem has been a failure in sending I2C reliably through PIO pins. If not, could the level shifter on this adapter be causing my problems? The THDB-H2S uses the regular HSMC I2C pins for accessing EEPROM storage on the adapter. Any help with this would be greatly appreciated.17 Replies
Altera_ForumWithout knowing the level shifter details, I can't say. There are different devices in use for this pupose. I don't even know the I2C voltage level at the camera module.
- Altera_Forum
I'm not sure how I missed this, but the camera I am interfacing with does have 1k resistors pulling up the sda and scl lines to 3.3 V.
I am having some success reading from the camera if I slow it down far enough, but not consistently. Writing to the board never seems to work though. I looked into the schematic of some generic i2c level shifters online, and they seem to use a pull up resistor on either side of the conversion. Ie, up to 2.5 on the fpga side, and up to 3.3 on the slave. It seems that now I have to figure out how to get an external resistor hooked up to the fpga side. Unfortunately this seems impossible... - Altera_Forum
I don't have schematics or other documentation of the said daughter board. Technical, you can place the pull-up anywhere at the I2C bus. This results from the fact, that the resistor value is high compared to trace impedances.
I guess, there should be a place, where you can solder an SMD chip or leaded resistor. I also don't know, why the board designers didn't think about this issue. But there's definitely no software method to replace a regular I2C pull-up, except for considerably slowing down the transmission speed, as said. - Altera_Forum
What I mean by where do I connect the pull up resistor is that the daughter board interfaces with an hsmc port and from there I am not able to access any pins along the i2c line.
I've noticed an option to define a pin as an external input... but how would I connect anything external to it? The only accessibly pins on this board are the hsmc ports or external clock. Anyone? - Altera_Forum
Ah I see.
I am a little cloudy on how I would go about using an external pull up. I suppose I would connect a 3.3V source behind a 1k-4.7k resistor connected to the i2c data line. But can I connect this anywhere along the signal path? Another idea: What if I turned off pci coupling and interfaced the boards as 3.3v - 3.3v? Might this reduce capacitance from level shifting and help the internal weak pull up to work? - Altera_Forum
Weak pull-ups are definitely too weak for regular I2C speed at some load capacitance. They can't be set to a higher strength. You should use external resistors of 1K to 4.7K maximum. As said, for SCL a push-pull driver can be used instead for most I2C applications, so basically an approriate SDA pull-up is what you need urgently.
- Altera_Forum
Are there any parameters or tricks one can use to "tweak" the pull up values that Quartus II implements on the Cyclone fpga's?
Or if not, what would be the best way to implement i2c using my own resistors? I am using an EP3C120F780C7 in a video development kit - Altera_Forum--- Quote Start --- You didn't tell about the used pull-up value. How can we determine, if it's appropriate? Furthermore, it has been said, that SCL can be driven by a push-pull output in most cases. Exactly, if only one I2C master exists (obviously) and the slave doesn't uitilize clock stretching (very likely, but you can check in the datasheet). --- Quote End --- Honestly, I am not that experienced with i2c or fpga's in general so please bare with my ignorance as I work through this. I am not using any external resistors (I don't even see how I could). The pull up value is whatever the "Weak pull up resistor" refers to in the Quartus II Assignment editor. How would I utilize push-pull? --- Quote Start --- Tell us also if you have used capacitors on the two SCL_CAM and SDA_CAM lines, and if yes, which values you used. Also be careful about the current drive strength on the two FPGA pins, it could be too high. Try to reduce the drive strength to lower values. --- Quote End --- The lines include a level conversion from 2.5 to 3.3 V (hsmc - santa cruz adapter - see my earlier post) which may introduce stray capacitance onto the line. Unfortunately there is no detailed schematic for the Terasic converter. How would I go about reducing the drive strength?
- Altera_Forum
Tell us also if you have used capacitors on the two SCL_CAM and SDA_CAM lines, and if yes, which values you used. Also be careful about the current drive strength on the two FPGA pins, it could be too high. Try to reduce the drive strength to lower values.
- Altera_Forum
You didn't tell about the used pull-up value. How can we determine, if it's appropriate? Furthermore, it has been said, that SCL can be driven by a push-pull output in most cases. Exactly, if only one I2C master exists (obviously) and the slave doesn't uitilize clock stretching (very likely, but you can check in the datasheet).
