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You didn't tell about the used pull-up value. How can we determine, if it's appropriate? Furthermore, it has been said, that SCL can be driven by a push-pull output in most cases. Exactly, if only one I2C master exists (obviously) and the slave doesn't uitilize clock stretching (very likely, but you can check in the datasheet).
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Honestly, I am not that experienced with i2c or fpga's in general so please bare with my ignorance as I work through this.
I am not using any external resistors (I don't even see how I could). The pull up value is whatever the "Weak pull up resistor" refers to in the Quartus II Assignment editor. How would I utilize push-pull?
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Tell us also if you have used capacitors on the two SCL_CAM and SDA_CAM lines, and if yes, which values you used. Also be careful about the current drive strength on the two FPGA pins, it could be too high. Try to reduce the drive strength to lower values.
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The lines include a level conversion from 2.5 to 3.3 V (hsmc - santa cruz adapter - see my earlier post) which may introduce stray capacitance onto the line. Unfortunately there is no detailed schematic for the Terasic converter.
How would I go about reducing the drive strength?
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