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Altera_Forum
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17 years ago

Help: HSMC and I2C

I am having a hell of a time trying to interface a camera through an HSMC - Santa Cruz adapter board (THDB-H2S - http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=39&no=219)

On a typical HSMC connector, are the I2C pins electrically different than PIO pins? If so this would indicate that my problem has been a failure in sending I2C reliably through PIO pins.

If not, could the level shifter on this adapter be causing my problems?

The THDB-H2S uses the regular HSMC I2C pins for accessing EEPROM storage on the adapter.

Any help with this would be greatly appreciated.

17 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I also got problem when I configing the I2C device through the HSMC connector.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Now I'am sure the key is not about the HSMC, I interfaced an I2C component through an HSMC successfully. Did you use pull-up resistance on the SDA and SCL on the board? And you can try to define the SDA and scl pins as "weak pull up resistor " in the assignment edit.

    Wish this help
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    With weak pull-up, SDA and SCL rise time may be too slow. You can slow down the I2C master timing in this case or use external strong pull-ups. They should me connected to 3.3V VCC to achieve a higher level without level translation. SCL could also use a push-pull driver, if no clock stretching is implemented by the slave. (Most likely it is neither used by the slave nor supported by the master).

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    --- Quote Start ---

    SCL could also use a push-pull driver, if no clock stretching is implemented by the slave. (Most likely it is neither used by the slave nor supported by the master).

    --- Quote End ---

    I would definitely try using push-pull for the I2C clock.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I've recently resurrected this project after taking a needed break. Unfortunately my situation is similar.

    I've been able to view the clock and data signals using a logic analyzer and their appears to be interference on the lines. For example, the data line will blip low at random intervals. This translates into incorrect bits being received on either end.

    Could this be a problem with the pull up resistor not being large enough? Anyone had similar problems?

    Thanks
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    You didn't tell about the used pull-up value. How can we determine, if it's appropriate? Furthermore, it has been said, that SCL can be driven by a push-pull output in most cases. Exactly, if only one I2C master exists (obviously) and the slave doesn't uitilize clock stretching (very likely, but you can check in the datasheet).

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Tell us also if you have used capacitors on the two SCL_CAM and SDA_CAM lines, and if yes, which values you used. Also be careful about the current drive strength on the two FPGA pins, it could be too high. Try to reduce the drive strength to lower values.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    --- Quote Start ---

    You didn't tell about the used pull-up value. How can we determine, if it's appropriate? Furthermore, it has been said, that SCL can be driven by a push-pull output in most cases. Exactly, if only one I2C master exists (obviously) and the slave doesn't uitilize clock stretching (very likely, but you can check in the datasheet).

    --- Quote End ---

    Honestly, I am not that experienced with i2c or fpga's in general so please bare with my ignorance as I work through this.

    I am not using any external resistors (I don't even see how I could). The pull up value is whatever the "Weak pull up resistor" refers to in the Quartus II Assignment editor. How would I utilize push-pull?

    --- Quote Start ---

    Tell us also if you have used capacitors on the two SCL_CAM and SDA_CAM lines, and if yes, which values you used. Also be careful about the current drive strength on the two FPGA pins, it could be too high. Try to reduce the drive strength to lower values.

    --- Quote End ---

    The lines include a level conversion from 2.5 to 3.3 V (hsmc - santa cruz adapter - see my earlier post) which may introduce stray capacitance onto the line. Unfortunately there is no detailed schematic for the Terasic converter.

    How would I go about reducing the drive strength?