HELP!! HOW TO WIRE 2 .vhd FILES!!!! IN QUARTUS!

Hey everybody

I have designed my own microprocessor (upro.vhd) in VHDL and my own(proper) memory(report) RAM of 256x4bits with QUARTUS II 9.0 (ram256x4.vhd), but I have a problem, I need to connect the DATA BUS and the ADDRESSES BUS of both files .vhd,

In the file up.vhd my ports are:

entity upro is

port (

clk: in std_logic;

Rst: in std_logic;

R_w: out std_logic;

dir: out std_logic_vector (7 downto 0);

dat: inout std_logic_vector (3 downto 0)

);

end upro;

.

.

.

signal a: std_logic_vector(3 downto 0);

signal carga_a: std_logic_vector(3 downto 0);

signal pc: std_logic_vector(7 downto 0);

signal carga_pc: std_logic_vector(7 downto 0);

signal rdat_in: std_logic_vector(3 downto 0);

signal dat_in: std_logic_vector(3 downto 0);

signal dat_out: std_logic_vector(3 downto 0);

signal rwaux: std_logic;

signal presente: estado:= inicial;

-----------------------------------------------------

In the file ram256x4.vhd my ports are:

entity ram256x4 is

port (

Clock: in std_logic;

OE: in std_logic;

RW: in std_logic;

CS: in std_logic;

RW_Addr: in std_logic_vector (7 downto 0); Data_A: inout std_logic_vector (3 downto 0);

Data_B: in std_logic_vector (3 downto 0);

);

end ram256x4;

.

.

.

signal tmp_ram: ram_type;

What I need is to connect (like wire)the ports:

Clk -------- Clock

RW_Addr ---- dir

dat -------- DATA_A

RW --------- r_w

How can I do this wire connection in vhdl?

Somebody told my I need a new .vhd to call both .vhd archives using PORT MAP… BUT I DON’T KNOW HOW IT WORKS!