HELP!! HOW TO WIRE 2 .vhd FILES!!!! IN QUARTUS!

You can also connect both components by wire signals. But if no external signals are generated by them, they are simply discarded

during Quartus synthesis. You have to use a VHDL simulator (e.g. ModelSim Altera Edition) to compile and simulate a design that

doesn't generate output signals.

Furthermore, I see that your RAM component has only inputs but no outputs. Something is obviously wrong with it.

If you want to show example designs, you should them upload as attachment with your posts.